AR# 47365: Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.3 (AXI) - Release Notes and Known Issues for ISE Design Suite 14.1
AR# 47365
Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.3 (AXI) - Release Notes and Known Issues for ISE Design Suite 14.1
Description
This Answer Record contains the Release Notes for the Virtex-6 FPGA LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v2.3, which was released in ISE Design Suite 14.1, and includes the following:
General Information
New Features
Supported Devices
Resolved Issues
Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.
Solution
General Information
Supports automatic generation of HDL wrapper files for the Virtex-6 FPGA Tri-Mode Ethernet MAC
Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII, and 1000Base-X PCS/PMA configurations are supported)
Provides a FIFO-based example design
Provides a demonstration testbench for the selected configuration
When configured for half-duplex operation, the provided example AXI4-Stream TX FIFO may corrupt the retransmitted frame following collision back-off. - CR 627016
Known Issues
(Xilinx Answer 40028) When using Virtex-6 Lower Power devices (-1L speed grade), implementation of the GMII physical interface fails to meet the receiver timing specification, and implementation of the RGMII physical interface results in little to no slack
(Xilinx Answer 47364) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Example Design Simulation Timeout using Modelsim 10.1a
(Xilinx Answer 43338) Virtex-4/Virtex-5/Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Configured for MII, GMII, or RGMII operation at 10 Mbps, MDIO transactions errors can occur
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AR# 47365
Date
04/23/2012
Status
Active
Type
Known Issues
IP
Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper