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AR# 47372

MIG 7 Series - Designs fail during MAP stage when XST option "KEEP_HIERARCHY" is set to "YES"

Description

Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

If the synthesis option "KEEP_HIERARCHY" is set to "YES" the MIG 7 Series designs will fail during the MAP stage with an error similar to the following:


ERROR:MapLib:1121 -
u_mig_7series_v1_5/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wra
pper/gen_dqs_iobuf_default.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs/OBUFTDS
is driven by
u_mig_7series_v1_5/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wra
pper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_la
ne_B/ddr_byte_group_io/dqs_gen.oddr_dqs (Q pin) and
u_mig_7series_v1_5/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wra
pper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_la
ne_B/ddr_byte_group_io/dqs_gen.oddr_dqsts (Q pin), but they are not all in the same level of hierarchy. Please ensure that any OBUF(T)DS with differential IOSTANDARD that is driven by a register or OSERDES exists in the same level of hierarchy as its drivers. This may be achieved by setting KEEP_HIERARCHY=FALSE on those levels of hierarchy separating the OBUF(T)DS from its drivers.

Solution

Setting "KEEP_HIERARCHY" to "YES" is not supported for MIG 7 Series designs.

To work around the issue, KEEP_HIERARCHY=NO can be set locally for the MIG design.

Here is some example syntax for setting the KEEP_HIERARCHY option locally in the RTL:

KEEP_HIERARCHY Verilog Example:
 
On Instance:
(* keep_hierarchy = "no" *) example_design u0_example_design (.dq(dq), .dqs)dqs), ...);

KEEP_HIERARCHY VHDL Example:
 
On Instance:
attribute keep_hierarchy : string;
attribute keep_hierarchy of u0_example_design : label is "no";
AR# 47372
Date Created 04/23/2012
Last Updated 08/13/2014
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series