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AR# 47383

MIG 7 Series DDR2/DDR3 (2:1 Mode) - Timing violations on phy_control paths may occur when interface is spread across 3 banks

Description

Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

The MIG 7 Series DDR23/DDR2 design may exhibit timing errors when implementing a design that is spread across 3 banks in 2:1 mode.

The timing errors are seen on the phycontrol path and are documented in this answer record.

Solution

Example Timing Errors:
 

--------------------------------------------------------------------------------
Slack (setup path): -0.092ns (requirement - (data path - clock path skew + uncertainty))
Source: u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_control_i (OTHER)
Destination: u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.ddr_phy_4lanes/phy_control_i (OTHER)
Requirement: 3.750ns
Data Path Delay: 3.332ns (Levels of Logic = 1)
Clock Path Skew: -0.444ns (1.153 - 1.597)
Source Clock: clk rising at 0.000ns
Destination Clock: clk rising at 3.750ns
Clock Uncertainty: 0.066ns

Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.110ns
Phase Error (PE): 0.000ns

Maximum Data Path at Slow Process Corner: u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_control_i to u_mig_7series_v1_4/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.ddr_phy_4lanes/phy_control_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------------ -------------------
PHY_CONTROL_X0Y7.PHYCTLFULL Tpctcko_FULL 0.342 u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_control_i
u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_control_i
SLICE_X0Y337.A6 net (fanout=2) 1.354 u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/_phy_ctl_full_p<0>
SLICE_X0Y337.A Tilo 0.049 u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_wd_of<25>
u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/wr_en_out1
PHY_CONTROL_X0Y5.PHYCTLWRENABLE net (fanout=3) 1.239 u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_wr_of
PHY_CONTROL_X0Y5.PHYCLK Tpctckd_WRN 0.348 u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.ddr_phy_4lanes/phy_control_i
u_mig_7series/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.ddr_phy_4lanes/phy_control_i
------------------------------------------------------------ ---------------------------

 

It is possible to work around these timing violations by adding an AREA_GROUP constraint to the failing OUT_FIFO/PHY_CONTROL, pre-FIFO path. 

The following constraints can be added to the MIG generated UCF:


INST "*/ddr_phy_4lanes_2.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" AREA_GROUP=lane2_bytea_outfifo;
INST "*/ddr_phy_4lanes_2.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen*.u_ddr_of_pre_fifo*" AREA_GROUP=lane2_bytea_outfifo;
AREA_GROUP "lane2_bytea_outfifo" RANGE=SLICE_X0Y150:SLICE_X19Y199;

These constraints will be included by default in a future MIG release.
 
AR# 47383
Date Created 04/23/2012
Last Updated 08/21/2014
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series