AR# 47387


LogiCORE IP Serial RapidIO Gen2 v1.4 - New Features: ChipScope in Example Design, Addressable Memory Space and Statistics Capture


The following three new features have been added in LogiCORE IP Serial RapidIO Gen2 v1.4. Details on these features have not been added in the product guide for the core in this release. It will be available in the next release of the product guide.

  • ChipScope in Example Design
  • Addressable Memory Space
  • Statistics Capture


ChipScope Tool in Example Design

ChipScope toolis now available as part of the example design. It is useful for quickly creating packets of all types, as well as observing behaviors on the user interface. The example design project comes with calls for the ICON, IL, and VIO features. In order to enable these features in hardware, be sure to set the USE_CHIPSCOPE parameter to 1 in of srio_example_top.v. Note that it is not advised to use ChipScope tool as part of a simulation and should only be used in hardware. After programming, load the ChipScope project file provided under example_design/chipscope.

The VIO dashboard allows you to send single packet of your own FTYPE, TTYPE, and size. Click the GO button to issue the transaction. For write bursts, the outgoing data field will be repeated for the appropriate size. A continuous traffic mode is also available through the VIO as well. It will run as long as the Continuous Traffic Mode is set to 1. Note, do not attempt to issue single packets while in continuous traffic mode.

The example design self checks incoming packets to ensure they are the expected type and ID. If an error does occur, the Error LED will turn red on the VIO. The IL feature of ChipScope tool allows users to monitor traffic on the user interfaces by setting up triggers and viewing the resulting waveforms.

Addressable Memory Space

When using the example design, reading from most memory locations results in the return of a repeatable data pattern. However, a dedicated memory space has been made for location 'h12_xxxx. Any write to these locations will be stored in local memory, which may be retrieved at any time by issuing a follow-up read instruction. This feature may be found in srio_response_gen.v.

Statistics Capture

A set of statistics registers have been made available, which may be accessed through ChipScope tool or a standard design. Use these registers for statistics, debug, and measuring the health of the link. If using through ChipScope tool, set the desired address in the statistics address field. The desired register value will be returned realtime in the statistics data field. This featureis implemented insrio_statistics.v.

Statistics register address mapping:

4'h0 packets observed over the past 2^10 cycles
4'h1 packets observed over the past 2^20 cycles
4'h2 number of active cycles (tready & tvalid) on incoming port 1 over the past 2^10 cycles
4'h3 number of active cycles (tready & tvalid) on incoming port 2 over the past 2^10 cycles
4'h4 number of active cycles (tready & tvalid) on outgoing port 1 over the past 2^10 cycles
4'h5 number of active cycles (tready & tvalid) on outgoing port 2 over the past 2^10 cycles
4'h6 total pnas sent
4'h7 total pnas received
4'h8 total requests sent
4'h9 total requests received
4'ha disparity error count
4'hb not-in-table error count
4'hc total packet retries sent
4'hd total packet retries received

Revision History
05/06/2012 - Initial Release

AR# 47387
Date 05/16/2012
Status Active
Type Documentation Changes
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