AR# 47389

MIG 7 Series DDR3 - Multi-controller designs might fail timing in certain configurations

Description

Version Found: v1.5
Version Resolved and Other Known Issues: See (Xilinx Answer 45195).

Virtex-7 FPGA multi-controller designs of 5 controllers or more might fail timing in certain configurations only. 

The following timing failure can be seen:

Slack (setup path): -0.221 ns (requirement - (data path - clock path skew + uncertainty))

Source: u_mig_7series_v1_4/c0_u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_0 (FF)

Destination: u_mig_7series_v1_4/c0_u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo (RAM)



Artix-7 FPGA multi-controller designs of three controllers or more might fail timing in certain configurations only. 

The following timing failure can be seen:

Source: u_mig_7series_v1_4/c1_u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/rd_ptr_0 (FF)

Destination: u_mig_7series_v1_4/c1_u_memc_ui_top_std/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_RAMC_D1 (RAM)

Solution

Timing is met for the majority of multi-controller configurations, but there are currently no work-arounds for the above configurations.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45195 MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions N/A N/A
AR# 47389
Date 08/21/2014
Status Active
Type Known Issues
Devices
IP