Description

This example design allocates 4K of block RAM attached to the M_AXI_GP0 and monitored by the ChipScope tool.

The software then treats the memory as a "shareable device" or "strongly-ordered," and a Vivado Logic Analyzer shot provides the distance between two consecutives BVALID signals on the AXI port for THROUGHPUT.

Implementation Details
Design Type	PS and PL
SW Type	Standalone
CPUs	Single CPU @ 666.67MHz
PS Features	MMU
PL Cores	BRAM, ILA
Boards/Tools	ZC702
Xilinx Tools Version	Vivado 2015.1
Other details	FCLK @ 150MHz
Address Map
	Base Address	Size	Bus Interface
Block RAM	0x41200000	4K	S_AXI
Files Provided
zc702_ar47406_v2015_1.zip	Archived Vivado IPI project.
xdmaps_example_w_intr.c	Snippet of code.
zc702_ar47406.tcl	TCL script to create the IPI block design
Block Diagram

Solution

Step-by-Step Instructions

1. Import the archived design into Vivado or run zc702_ar47406.tcl to create the IPI project, then export to SDK.
2. In SDK, create a Hello World example.
3. Modify the Hello World example to include the snippet of C code.
4. Program the PL using the BITSTREAM generated by Vivado.
5. Set up ILA to trigger on the BVALID signal.
6. Run the application.
7. Measure the throughput as the time between two consecutive BVALID signals on the AXI Master Interface.
8. The memory access is driven by PS DMA. Burst length is 16.

Expected Results

Attachments

Associated Attachments

Linked Answer Records

Master Answer Records