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  1. Xilinx - All Programmable
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  3. AR# 47406: Zynq-7000 Example Design - CPU throughput to access an AXI Slave using Master AXI GP

AR# 47406

Zynq-7000 Example Design - CPU throughput to access an AXI Slave using Master AXI GP

Description

This example design allocates 4K of block RAM attached to the M_AXI_GP0 and monitored by the ChipScope tool.

The software then treats the memory as a "shareable device" or "strongly-ordered," and a Vivado Logic Analyzer shot provides the distance between two consecutives BVALID signals on the AXI port for THROUGHPUT.

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.

It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill their needs.

Limited support is provided by Xilinx on these Example Designs.
 

Implementation Details

Design Type

PS and PL

SW Type

Standalone

CPUs

Single CPU @ 666.67MHz

PS Features

MMU

PL Cores

BRAM, ILA

Boards/Tools

ZC702

Xilinx Tools Version

Vivado 2015.1

Other details

FCLK @ 150MHz

Address Map
 

Base Address

Size

Bus Interface

Block RAM

0x41200000

4K

S_AXI

Files Provided

zc702_ar47406_v2015_1.zip

Archived Vivado IPI project.

xdmaps_example_w_intr.c

Snippet of code.

zc702_ar47406.tcl

TCL script to create the IPI block design

Block Diagram


 

Solution

Step-by-Step Instructions

  1. Import the archived design into Vivado or run zc702_ar47406.tcl to create the IPI project, then export to SDK.
  2. In SDK, create a Hello World example.
  3. Modify the Hello World example to include the snippet of C code.
  4. Program the PL using the BITSTREAM generated by Vivado.
  5. Set up ILA to trigger on the BVALID signal.
  6. Run the application.
  7. Measure the throughput as the time between two consecutive BVALID signals on the AXI Master Interface.
  8. The memory access is driven by PS DMA. Burst length is 16.


Expected Results

 
Throughput
Type
FCLK Cycles
CPU Cycles
Time (nS)
Strongly-ordered      
Shareable device
16
0
106

Attachments

Associated Attachments

Name File Size File Type
xdmaps_example_w_intr.c 12 KB C
zc702_ar47406.tcl 9 KB TCL
zc702_ar47406_v2015_1.zip 135 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51779 Zynq-7000 AP SoC - Example Designs and Tech Tips N/A N/A
AR# 47406
Date 07/09/2015
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • Vivado Design Suite - 2015.1
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit