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AR# 47407

AXI4-Stream Interconnect - Release Notes and Known Issues

Description

This Release Note and Known Issues Answer Record is for , and contains the following information:

  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes GUI (XTP025).

Solution

General Information

The AXI4-Stream Interconnect IP is a powerful collection of modules that provides a rich set of functions for connecting together AXI4-Stream masters and slaves. The IP core is capable of performing data switching/routing, data width conversion, pipelining, clock conversation and data buffering. Parameters and IP configuration Graphical User Interfaces (GUIs) are used to configure the core to suit each of the system designer's requirements.

Software Requirements

New Features

v1.1

  • Support for ACLKEN across clock converters and FIFO.
  • Area improvements in data width converters.
  • Enhanced GUI layout.

Resolved Issues

Known Issues

This table correlates the core version to the first IDS software release version in which it was included.

Core Version
v1.1
IDS Version
14.2/2012.2
v1.0 14.1/2012.1

AR# 47407
Date Created 04/23/2012
Last Updated 07/23/2012
Status Active
Type Release Notes
Devices
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • More
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Virtex-7
  • Virtex-7 HT
  • Less
Tools
  • PlanAhead - 14.1
  • ISE Design Suite - 14.1
  • Vivado - 2012.1
IP
  • AXI Interconnect