The Design Assistant walks you through the recommended design flow for Vivado HLS.
The Design Assistant not only provides useful design and troubleshooting information, but also points you to the exact documentation you need to read to help you design efficiently with Vivado High-Level Synthesis.
Note: This answer record is part of the Xilinx Vivado HLS Solution Center (Xilinx Answer 47428).
The Xilinx Vivado HLS Solution Center is available to address all questions related to Vivado HLS.
Free video trainings are available at the Xilinx Training site:
Vivado High-Level Synthesis Training
Directive Behaviors
| (Xilinx Answer 60923) | Design Assistant for Vivado HLS : Understanding the Vivado HLS Design Flow |
| (Xilinx Answer 60924) | Design Assistant for Vivado HLS : C Code and Vivado HLS |
| (Xilinx Answer 60925) | Design Assistant for Vivado HLS : Design Analysis and Optimization |
| (Xilinx Answer 60926) | Design Assistant for Vivado HLS : RTL Verification |
| (Xilinx Answer 60927) | Design Assistant for Vivado HLS : Integrating HLS IP into the System |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47428 | Xilinx Vivado HLS Solution Center | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 44786 | AutoESL - Sharing of internal AP_STREAMs and scope | N/A | N/A |
| 47509 | Vivado HLS 2012.2: Why is the AP_ready port not written out? | N/A | N/A |
| 50929 | AutoESL - Zynq SoC Design Example with AXI-DMA Core for Data Transfer | N/A | N/A |
| 59678 | Vivado HLS 2013.4, 2014.1: FFT, FIR designs and examples: incorrect values are reported and are not updated | N/A | N/A |
| 60923 | Design Assistant for Vivado HLS : Understanding the Vivado HLS Design Flow | N/A | N/A |
| 60924 | C Code and Vivado HLS | N/A | N/A |
| 60925 | Vivado HLS : Design Analysis and Optimization | N/A | N/A |
| 60926 | Vivado HLS : RTL Verification | N/A | N/A |
| 60927 | Vivado HLS : Integrating HLS IP into the System | N/A | N/A |
| 61063 | Vivado HLS 2014.2: Debug Guide for investigating C/RTL co-simulation issues | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47429 | Xilinx Vivado HLS Solution Center - Top Issues | N/A | N/A |
| 47432 | Xilinx Vivado HLS Solution Center - Documentation | N/A | N/A |
| 47433 | Design Advisory Master Answer Record for Xilinx Vivado HLS Tool | N/A | N/A |
| AR# 47431 | |
|---|---|
| Date | 07/17/2019 |
| Status | Active |
| Type | Solution Center |
| Tools | |