UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47441

Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7

Description

This Release Notes and Known Issues Answer Record is for Virtex-7 FPGA Gen3 Integrated Block for PCI Express, first released in the ISE 14.1 and Vivado 2012.1 design suites, and contains the following information:

  • General Information
  • New Features
  • Supported Devices
  • Known Issues

For installation instructions, general CORE Generator tool known issues, and design tools requirements, see the IP Release Notes Guide.
Documentation for this core can be found at: http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express.htm

Solution

General Information

  • The ISE 14.7 design suite release contains the v1.7 of the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core.
  • For release notes on v2.2 of the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core, see (Xilinx Answer 54645).
  • For information related to 7 series Integrated Block for PCI Express (Gen2) core, see (Xilinx Answer 40469).
  • For 7 series FPGAs GTX/GTH transceivers known Issues and answer record list, check (Xilinx Answer 37179).

New Features

  • ISE 14.7 design tool support

Supported Devices

  • Virtex-7 XT
  • Devices implemented with stacked silicon interconnect (SSI) technology are not supported. Customers wanting to target SSI technology (1140T) must use the Vivado design tools development environment.
Note: For the previous versions "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

Known Issues


Core Version
Vivado Tools Version
ISE Tools Version
v1.7 NA 14.7
v1.6 NA 14.6
v1.5 NA 14.5
v1.4 2012.4 14.4
v1.3 2012.3 14.3
v1.2 2012.2 14.2
v1.1 Rev1 2012.1.1 14.1.1
v1.1
2012.1
14.1

For 7-Series FPGA Errata, please check : http://www.xilinx.com/support/documentation/7_series_errata.htm.

The following table provides known issues for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express.

Article Number Article Title Version Found Version Resolved
(Xilinx Answer 56057) (Vivado 2012.4) - Core may reply with an incorrect value for the Configuration Read Request to the Device ID v1.4 v2.0
(Xilinx Answer 55309)

ERROR:Place:1340 - PAD.pci_exp_rxn<1> is tied to GTHE_CHANNEL.pcie3_7x_v1_4_i/inst/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1]

v1.5 v1.6
(Xilinx Answer 54174) (ISE 14.4/Vivado 2012.4) - GTX transceiver CPLL can become inoperative on certain conditions v1.4 Silicon Revision Dependent
(Xilinx Answer 53740) (ISE 14.4 / 2012.4) - No Clock Output on TXOUTCLK at Cold Temperature v1.4 v1.5
(Xilinx Answer 53371) (ISE 14.4) - Support for VC709 Xilinx Development Board v1.4 v1.5
(Xilinx Answer 53312) (Vivado 2012.4/ISE 14.4) - Support for IES devices v1.4 Not Resolved Yet
(Xilinx Answer 53023) (Vivado 2012.4) - WARNING: [Vivado 12-180] No cells matched / CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. v1.4 v2.0
(Xilinx Answer 53151) (ISE 14.3/ Vivado 2012.3) - Rate change back to Gen3 speed fails on x79 motherboard v1.3 Not Resolved Yet
(Xilinx Answer 52275) (2012.3) - Virtex-7 1140T IES device support v1.3 v1.4
(Xilinx Answer 52497) (ISE 14.3) - Initial VF and Total VF value of 0 in a physical function is not allowed with SR-IOV enabled v1.3 v1.5
(Xilinx Answer 52449) (ISE 14.3 / Vivado 2012.3) - Root Port Configuration Support v1.3 v1.5
(Xilinx Answer 50837) (ISE 14.2/Vivado 2012.2) - Some features in Endpoint Configuration not verified v1.2 Not Resolved Yet
(Xilinx Answer 50333) (ISE 14.1/Vivado 2012.1) - Core Configuration GUI incorrectly selects 62.5Mhz for x4, 2.5GT/s and 64-bit Interface Width v1.1 v1.2
(Xilinx Answer 50312) (ISE 14.1 / Vivado 2012.1) - The core does not transmit Memory Read TLPs upstream v1.1 v1.2
(Xilinx Answer 50276) (Vivado 2012.1) - Incorrect Capability Pointer Value v1.1 v1.2
(Xilinx Answer 50189) (ISE 14.1 / Vivado 2012.1) - Default value for TX Preset Settings not used v1.1
v1.2
(Xilinx Answer 50188) (ISE 14.1 / Vivado 2012.1) - The core does not come out of the Disabled state v1.1 v1.1 Rev1/v1.2
(Xilinx Answer 50232) (ISE 14.1 / Vivado 2012.1) - Secondary PCI Express Extended Capability not enabled by default in Gen3 core configuration v1.1 v1.3
(Xilinx Answer 50183) (ISE 14.1 / Vivado 2012.1) - User clock frequency is fixed and not selectable in the core configuration GUI v1.1 v1.4
(Xilinx Answer 50228) (ISE 14.1 / Vivado 2012.1) - Incorrect core functionality when performance level is set to 'Extreme' in Gen1/Gen2 core configuration v1.1 v1.2
(Xilinx Answer 47876) (ISE 14.1 / Vivado 2012.1) - Supported Simulators v1.1 v1.2
(Xilinx Answer 47604) (ISE 14.1 / Vivado 2012.1) - Incorrect Byte Count set when responding to Poisoned AtomicOp Request v1.1 Not Resolved Yet
(Xilinx Answer 47610) (ISE 14.1 / Vivado 2012.1) - Address Aligned mode is unsupported with the default example design v1.1 v1.4
(Xilinx Answer 47613) (Vivado 2012.1) - XSIM flow is not supported v1.1 v1.2
(Xilinx Answer 47614) (ISE 14.1 / Vivado 2012.1) - Legacy Endpoint configuration not supported in the example design. v1.1 v1.3
(Xilinx Answer 47615) (ISE 14.1 / Vivado 2012.1) - Timing Violations observed in certain IP configurations. v1.1 Not Resolved Yet

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Other Information:

Revision History

05/08/2012 - Initial release
05/15/2012 - Added (Xilinx Answer 47876)
05/30/2012 - Added (Xilinx Answer 50183)
06/06/2012 - Updated for ISE 14.1/Vivado 2012.1 Device Pack Release
07/25/2012 - Updated for ISE 14.2/Vivado 2012.2
08/02/2012 - Changed "Version Resolved" for (Xilinx Answer 50232)
10/23/2012 - Updated for ISE 14.3/Vivado 2012.3
11/16/2012 - Added (Xilinx Answer 52275)
11/28/2012 - Added (Xilinx Answer 53151)
11/29/2012- Removed (Xilinx Answer 47611)
12/18/2012 - Updated for ISE 14.4/Vivado 2012.4
01/21/2013 - Added (Xilinx Answer 53740)
02/22/2013 - Added (Xilinx Answer 54174)
04/03/2013 - Updated for ISE 14.5
05/17/2013 - Added (Xilinx Answer 56057)
06/19/2013 - Updated for ISE 14.6
10/03/2013 - Added (Xilinx Answer 57777)
10/23/2013 - Updated for ISE 14.7

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51901 Virtex-7 FPGA VC709 Connectivity Kit - Known Issues and Release Notes Master Answer Record N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
47674 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Virtual Channel Capability is always enabled N/A N/A
47671 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Incorrect reset of ARI Capable Hierarchy bit in the SR-IOV control register N/A N/A
47670 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Incorrect reset value of the TC/VC Map field in the Virtual Channel Resource Control register N/A N/A
47668 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - AER Header Log Overflow Status Bit Support N/A N/A
47614 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Example Design Legacy Endpoint Configuration Support N/A N/A
47613 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (Vivado 2012.1) - XSIM flow Support N/A N/A
47612 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1) - SSIT device support in the CORE Generator tool N/A N/A
47611 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Bit File Generation Support N/A N/A
47610 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Address Aligned Mode Support in Default Example Design N/A N/A
47609 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - D1 low power device state support in IES silicon N/A N/A
47608 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - PF0_PM_CSR_NOSOFTRESET must be tied to 1'b1 in IES Silicon N/A N/A
47607 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - TLP Processing Hints (TPH) support in IES Silicon N/A N/A
47606 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - ECRC support in IES Silicon N/A N/A
47605 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - RBAR support in IES Silicon N/A N/A
47604 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Incorrect Byte Count set when responding to Poisoned AtomicOp Request N/A N/A
50232 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1/Vivado 2012.1) - Secondary PCI Express Extended Capability not enabled by default in Gen3 Core Configuration N/A N/A
50228 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1/Vivado 2012.1) - Incorrect Core Functionality when Performance Level is set to 'Extreme' in Gen1/Gen2 Core Configuration N/A N/A
50276 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (Vivado 2012.1) - Incorrect Capability Pointer Value N/A N/A
50312 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - The Core does not Transmit Memory Read TLPs Upstream N/A N/A
50333 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1/Vivado 2012.1) - Core Configuration GUI Incorrectly Selects 62.5 MHz for x4, 2.5 GT/s and 64-bit Interface Width N/A N/A
52449 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 (ISE 14.3 / Vivado 2012.3) - Root Port Configuration Support N/A N/A
52497 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 (ISE 14.3) - Initial VF and Total VF value of 0 in a physical function is not allowed with SR-IOV enabled N/A N/A
53312 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 (Vivado 2012.4/ISE 14.4) - Support for IES Devices N/A N/A
53371 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 (ISE 14.4) - Support for VC709 Xilinx Development Boards N/A N/A
53747 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 - Incorrect RXCDR_CFG attributes in GTH results in non-working link N/A N/A
54902 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - IES/GES Devices Support in Vivado 2013.1 and ISE Design Suite 14.5 N/A N/A
56057 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 [Vivado 2012.4] - Core may reply with an incorrect value for the Configuration Read Request to the Device ID N/A N/A
AR# 47441
Date Created 05/04/2012
Last Updated 11/01/2013
Status Active
Type Release Notes
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)