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AR# 47459

SPI-4.2 v10.6 - Release Notes and Known Issues for ISE Design Suite 14.1

Description

This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v10.6 Core released in ISE Design Suite 14.1), and contains the following information:
  • New Features
  • Supported Devices
  • Resolved Issues
  • General Information
  • Known Issues

For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features
  • ISE 14.1 software support

Supported Devices

  • Virtex-4, Virtex-5, Virtex-6, and Virtex-6L FPGA
Resolved Issues
  • (Xilinx Answer 42573) - SPI-4.2: Timing errors seen when performance is 1.2 Gb/s and the TSClk is on global clocking.

Known issues

  • Spartan-6 FPGA support has been removed in ISE 12.4 onwards
    Description: Users cannot target Spartan-6 devices when using the SPI-4.2 core.
    Workaround: Use an alternative device like Virtex-6 CXT. (Xilinx Answer 39106)
AR# 47459
Date Created 05/29/2012
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • SPI-4 Phase 2 Interface Solutions