There is a possibility to have a deadlock on the PS AXI interconnect when an AXI_HP source and another source, such as the DMAC, each generates accesses to both the OCM and DDR in an inter-dependent way.
Deadlock can be avoided by having one of the sources make requests to only one destination (OCM or DDR) or restrict the number of outstanding writes by an AXI_HP interface to one write at a time.
The problematic sources include the pairs of AXI_HP interfaces and the Central Interconnect (DMAC, IOP masters, etc.). The APU memory requests (CPUs and ACP) are not problematic.
Impact: | Major. The system can hang. |
Work-arounds: | Please see Article Details section. |
Configurations Affected: | Designs using AXI_HP interfaces |
Device Revision(s) Affected: | Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record |
The deadlock condition can occur when two sources are accessing the OCM and DDR in a certain sequence. There are three sources that can affect the deadlock condition. The sources do NOT include memory requests from the APU (CPUs and ACP interface).
Any combination of two of these sources each accessing both OCM and DDR can cause the deadlock condition:
Central Interconnect (includes DMAC, IOP masters, etc.)
AXI_HP{1:0} includes, for example, AXI_HP0 accessing OCM and AXI_HP1 accessing DDR (both masters are in the same HP pair).
Examples of when deadlock will NOT occur:So, again, for the deadlock condition to occur, two sources must both be accessing OCM and DDR.
One of the sources must be one of the AXI_HP pairs. The other source can be the other AXI_HP pair or masters connected to the Central Interconnect.
In addition to each of the two source accessing both OCM and DDR, they need to do the accesses in a specific sequence order.
Here is a specific example that shows the sequence:
AXI_HP Master | DMA Controller Master |
AXI_HP_DDR1_1 (to DDR port 1) | DMA_OCM (to OCM) |
AXI_HP_DDR1_2 (to DDR port 1) | DMA_ DDR2 (to DDR port 2) |
AXI_HP_OCM (to OCM) |
Write address and write data travel on separate channels independently; however, at the slave, write data order has to follow the write address sequence accepted by the slave, i.e. no re-ordering is allowed.
Here is a possible ordering of transactions as seen by the DDR:
As can be seen from the above, deadlock occurs.
Work-around Info: There are a couple of work-arounds for this problem:
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
53051 | Zynq-7000 SoC - PS DDR Controller | N/A | N/A |
AR# 47484 | |
---|---|
Date | 06/13/2018 |
Status | Active |
Type | Design Advisory |
Devices |