Description

There is a possibility to have a deadlock on the PS AXI interconnect when an AXI_HP source and another source, such as the DMAC, each generates accesses to both the OCM and DDR in an inter-dependent way. Deadlock can be avoided by having one of the sources make requests to only one destination (OCM or DDR) or restrict the number of outstanding writes by an AXI_HP interface to one write at a time. The problematic sources include the pairs of AXI_HP interfaces and the Central Interconnect (DMAC, IOP masters, etc.). The APU memory requests (CPUs and ACP) are not problematic.

Solution

The deadlock condition can occur when two sources are accessing the OCM and DDR in a certain sequence. There are three sources that can affect the deadlock condition. The sources do NOT include memory requests from the APU (CPUs and ACP interface).

• AXI_HP{1,0} as a pair
• AXI_HP{3,2} as a pair

Central Interconnect (includes DMAC, IOP masters, etc.)

AXI_HP{1:0} includes, for example, AXI_HP0 accessing OCM and AXI_HP1 accessing DDR (both masters are in the same HP pair).

• The AXI_HP pair is not accessing both OCM and DDR
• The Central Interconnect is not accessing both the OCM and DDR
• AXI_HP0 is accessing OCM and AXI_HP3 is accessing DDR (different AXI_HP pairs)

In addition to each of the two source accessing both OCM and DDR, they need to do the accesses in a specific sequence order.

Here is a specific example that shows the sequence:

• AXI_HP_DDR1_1: 1st write from AXI_HP was successful.
• DMA_DDR2:The DDRC accepts the transaction, but cannot complete it because write data is not available until after DMA_OCM
• AXI_HP_DDR1_2: DDR cannot process this until DMA_DDR2 is complete

• AXI_HP_OCM: OCM accepts the transaction, but cannot complete it because write data is not available until after AXI_HP_DDR1_2 completes.
• DMA_OCM: OCM cannot process this until AXI_HP_OCM completes.

Linked Answer Records

Master Answer Records