AR# 47484


Zynq-7000 SoC, AXI - Deadlock Can Occur when OCM and DDR are Accessed by AXI_HP


There is a possibility to have a deadlock on the PS AXI interconnect when an AXI_HP source and another source, such as the DMAC, each generates accesses to both the OCM and DDR in an inter-dependent way. 

Deadlock can be avoided by having one of the sources make requests to only one destination (OCM or DDR) or restrict the number of outstanding writes by an AXI_HP interface to one write at a time. 

The problematic sources include the pairs of AXI_HP interfaces and the Central Interconnect (DMAC, IOP masters, etc.). The APU memory requests (CPUs and ACP) are not problematic.


Impact: Major. The system can hang.
Work-arounds:Please see Article Details section.
Configurations Affected: Designs using AXI_HP interfaces
Device Revision(s) Affected:Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record


The deadlock condition can occur when two sources are accessing the OCM and DDR in a certain sequence. There are three sources that can affect the deadlock condition. The sources do NOT include memory requests from the APU (CPUs and ACP interface).

Any combination of two of these sources each accessing both OCM and DDR can cause the deadlock condition:


  • AXI_HP{1,0} as a pair
  • AXI_HP{3,2} as a pair

Central Interconnect (includes DMAC, IOP masters, etc.)

AXI_HP{1:0} includes, for example, AXI_HP0 accessing OCM and AXI_HP1 accessing DDR (both masters are in the same HP pair).

Examples of when deadlock will NOT occur:

  • The AXI_HP pair is not accessing both OCM and DDR
  • The Central Interconnect is not accessing both the OCM and DDR
  • AXI_HP0 is accessing OCM and AXI_HP3 is accessing DDR (different AXI_HP pairs)

So, again, for the deadlock condition to occur, two sources must both be accessing OCM and DDR. 

One of the sources must be one of the AXI_HP pairs. The other source can be the other AXI_HP pair or masters connected to the Central Interconnect.

In addition to each of the two source accessing both OCM and DDR, they need to do the accesses in a specific sequence order.

Here is a specific example that shows the sequence:

AXI_HP MasterDMA Controller Master
AXI_HP_DDR1_1 (to DDR port 1)DMA_OCM (to OCM)
AXI_HP_DDR1_2 (to DDR port 1)DMA_ DDR2 (to DDR port 2)

Write address and write data travel on separate channels independently; however, at the slave, write data order has to follow the write address sequence accepted by the slave, i.e. no re-ordering is allowed. 

Here is a possible ordering of transactions as seen by the DDR:

  • AXI_HP_DDR1_1: 1st write from AXI_HP was successful.
  • DMA_DDR2:The DDRC accepts the transaction, but cannot complete it because write data is not available until after DMA_OCM
  • AXI_HP_DDR1_2: DDR cannot process this until DMA_DDR2 is complete
  Here is the ordering of transactions as seen by the OCM:
  • AXI_HP_OCM: OCM accepts the transaction, but cannot complete it because write data is not available until after AXI_HP_DDR1_2 completes.
  • DMA_OCM: OCM cannot process this until AXI_HP_OCM completes.

As can be seen from the above, deadlock occurs.

Work-around Info: There are a couple of work-arounds for this problem:

  • Ensure that the master pair of AXI_HP0/AXI_HP1 only accesses a single destination of OCM or DDR and the accesses from the master pair of AXI_HP2/AXI_HP3 are also restricted to only OCM or DDR.
  • Put a write issue limit on the AXI_HP ports of 1 outstanding transaction at a time. For writes, this can be accomplished by writing 0x0 to AFI_WRCHAN_ISSUINGCAP.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
53051 Zynq-7000 SoC - PS DDR Controller N/A N/A
AR# 47484
Date 06/13/2018
Status Active
Type Design Advisory
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