2. Support
  3. AR# 4751: 8.1i NGDBuild - "FATAL_ERROR...Pointer already registered. Process will terminate."
  4. AR# 47514: Zynq-7000 SoC, DDR - DDR3 Starts DRAM Clock too Early after Exiting Self-Refresh

AR# 47514

Zynq-7000 SoC, DDR - DDR3 Starts DRAM Clock too Early after Exiting Self-Refresh

Description

The user can program the DDR3 controller to enable Self-Refresh Clock-Stop mode. The controller correctly stops the clock to DRAM, but it does not satisfy the tCKSRE time (around 5 clock cycles) before restarting the clock.
Either do not use the DDR3 Self-Refresh mode or have software ensure that the enable/disable of the Self-Refresh is only done when there is no DRAM activity.

Solution

Impact:
Minor, see Work-around Details paragraphs.
Work-around:
Do not enable self-refresh clock stop mode or manually control the clock.
Configurations Affected:
Systems using the PS DDR controller in DDR3 mode with self-refresh.
Device Revision(s) Affected:Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record

When Self-Refresh Clock-Stop mode is enabled for DDR3 operation, the controller correctly stops the clock to DRAM; however, it does not satisfy the tCKSRE time (around 5 clock cycles) before restarting the clock. DDR3 clocks can be restarted too soon before the required delay period.
Work-around Details: If it is desired to disable the DDR3 clock dynamically to reduce power, the system needs to be aware when the DDR3 bus is going to be idle for a long time and manually set the clock stop feature when the Self Refresh is on. Here are the steps involved:
  • Enable the Self Refresh in the Controller.
  • Check whether the DDR bus is idle. One way to achieve this is to monitor if DDRC operating mode register is 2'b11, representing the Self Refresh mode.
  • Set the clock stop feature in the DDRC through register 0x08.
  • When the system senses that the traffic to DDRC is going to resume, it can reset the clock stop feature.
  • Controller automatically brings DRAM out of Self Refresh when data transfers to DDRC resume.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
53051 Zynq-7000 SoC - PS DDR Controller N/A N/A
AR# 47514
Date 05/23/2018
Status Active
Type Design Advisory
Devices