We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 47514: Zynq-7000 AP SoC, DDR - DDR3 Starts DRAM Clock too Early after Exiting Self-Refresh
Zynq-7000 AP SoC, DDR - DDR3 Starts DRAM Clock too Early after Exiting Self-Refresh
The user can program the DDR3 controller to enable Self-Refresh Clock-Stop mode. The controller correctly stops the clock to DRAM, but it does not satisfy the tCKSRE time (around 5 clock cycles) before restarting the clock.
Either do not use the DDR3 Self-Refresh mode or have software ensure that the enable/disable of the Self-Refresh is only done when there is no DRAM activity.
Minor, see Work-around Details paragraphs.
Do not enable self-refresh clock stop mode or manually control the clock.
Systems using the PS DDR controller in DDR3 mode with self-refresh.
When Self-Refresh Clock-Stop mode is enabled for DDR3 operation, the controller correctly stops the clock to DRAM; however, it does not satisfy the tCKSRE time (around 5 clock cycles) before restarting the clock. DDR3 clocks can be restarted too soon before the required delay period.
Work-around Details: If it is desired to disable the DDR3 clock dynamically to reduce power, the system needs to be aware when the DDR3 bus is going to be idle for a long time and manually set the clock stop feature when the Self Refresh is on. Here are the steps involved:
Enable the Self Refresh in the Controller.
Check whether the DDR bus is idle. One way to achieve this is to monitor if DDRC operating mode register is 2'b11, representing the Self Refresh mode.
Set the clock stop feature in the DDRC through register 0x08.
When the system senses that the traffic to DDRC is going to resume, it can reset the clock stop feature.
Controller automatically brings DRAM out of Self Refresh when data transfers to DDRC resume.