AR# 47516


Zynq-7000 SoC, DDR - Controller Mishandles STREX Instruction


Under certain circumstances with the cache disabled, the DDR Controller does not respond properly to an Exclusive Store (STREX) instruction executed by a CPU.

This can be avoided by executing the STREX instruction only in cacheable memory space with the cache enabled.


Impact: Minor, it is very rare that the system locks-up.

Work-around: If the masters that require the exclusive operations are limited to the ARM cores, by making the region that requires exclusive operations cacheable and having the L1 caches enabled, the problem can be prevented. Furthermore, if one of the masters happens to be in the PL, an Exclusive monitor can be implemented in the PL and the accesses from the ARM CPUs and the fabric master are routed to that monitor.

Configurations Affected: Systems that issue Exclusive operations to the DDR memory controller.

Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.

DDRC does not generate a proper response when it executes the STREX instruction under certain circumstances. The following sequence of exclusive operations demonstrates a scenario under which the STREX instruction gets mishandled.

  • Master 0 executes EXCL RD with address AEXOKAY (Correct)
  • Master 1 executes EXCL RD with address BEXOKAY (Correct)
  • Master 1 executes EXCL WR with address BEXOKAY (Correct)
  • Master 1 executes EXCL RD with address AEXOKAY (Correct)
  • Master 0 executes EXCL WR with address AOKAY (Incorrect)
  • Master 1 executes EXCL WR with address AEXOKAY (Incorrect)
In this sequence, Master 0 executes an Exclusive Read (LDREX) from address A. Before Master 0 executes the Exclusive Write (STREX) to the same address to complete the exclusive operation, Master 1 has issued a LDREX/STREX pair and completed an exclusive operation on address B followed by a LDREX from address A. In this case, Master 0 can still complete the exclusive operation on address A by executing the STREX to that address; however, this action does not reset the exclusive access monitor for Master 1; and therefore, a subsequent STREX instruction from Master 1 will receive an erroneous EXOKAY response, indicating that the Write operation by Master 1 was completed while it was not.

Impact Details:
This is a rare problem and does not manifest itself in the most common use case which is between the two ARM CPUs when the L1 caches are enabled. However, in a rare scenario when the caches are disabled, the exclusive access may be mishandled and, depending on its usage, it may create a lockup.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
53051 Zynq-7000 SoC - PS DDR Controller N/A N/A
AR# 47516
Date 06/13/2018
Status Active
Type Design Advisory
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