AR# 47518: Zynq-7000 SoC, SMC - Potential SRAM/NOR Data Error
Zynq-7000 SoC, SMC - Potential SRAM/NOR Data Error
A potential SRAM/NOR data error can occur if all the write data of a transaction is contained in a single AXI data transfer cycle. Always perform writes that require multiple AXI data transfer cycles in the transaction.
Minor, refer to the Work-around Details.
See Work-around Details.
Systems that use the SRAM/NOR interface. The NAND interface mode is unaffected.
Use a memory burst length that is long enough to contain more than one AXI beat (normally memory burst length of 4 will do this). This work-around has least impact on performance because AXI bursts of data (greater than 1 beat) are treated optimally on the memory interface. This work-around can be used provided the memory device supports back to back transactions without chip select being deasserted.
If the memory device requires chip select to be deasserted between bursts, then the best work-around is to set the refresh_period register to 1. This ensures the controller returns to idle between every transaction. This adds tTR idle cycles between each transaction of a burst that would otherwise have completed back to back.