There is a defect in the coding of the ECC algorithm and it misses single-bit errors to bit 0 of byte 0 and fails to detect some double-bit error cases. Only the odd half of the parity calculation is being tested to check for pass/fail. When reading the data from NAND with the ECC enabled, in some specific cases, the results indicated in the registers are incorrect.
|Impact:||Major. There are three implications, see the Impact Details paragraphs. The work-arounds greatly reduce the likelihood of missing errors.|
|Work-arounds:||Please see the Work-around Details.|
|Configurations Affected:||Systems that use ECC with NAND.|
|Device Revision(s) Affected:|
Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.
There are three implications:
There is a software work-around to the implication (1). If a single-bit error occurs to bit 0 of byte 0, the ECC register values return.
A more complex software work-around is to manually read the ECC parity data stored in the spare area, and then use software to calculate the ECC result independently of the hardware mechanism.ecc_fail = 0 and ecc_correct = 1. This result uniquely identifies a single bit error to bit 0 of byte 0. The register values can be read to identify this case, and the bit error can be corrected with software.