The DDR I/O buffer (DDRIOB) DCI impedance adjustment mode (slcr.DDRIOB_DCI_CTRL [UPDATE_CONTROL]) should be set according to the Calibration table in Chapter 10 of the TRM v1.5 or later.
Impact: | Trivial. |
Work-around: | None. |
Configurations Affected: | Systems that DDR in the PS. |
Device Revision(s) Affected: | Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences |
January 2013: slcr.DDRIOB_DCI_CTRL.UPDATE_CONTROL must be set to '0' for DCI operation, to allow the VRN/VRP to sample the reference resistors.
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
47916 | Zynq-7000 SoC Devices - Silicon Revision Differences | N/A | N/A |
AR# 47521 | |
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Date | 06/13/2018 |
Status | Active |
Type | Design Advisory |
Devices |