This answer record contains the Release Notes for the LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII and includes the following:
New Features for Latest v11.5 Core
Supported Devices for Latest v11.5 Core
Note: For a complete part and package support list, please check Xilinx CORE Generator interface (under 'Supported Families') for the Ethernet 1000BASE-X PCS/PMA or SGMII Core.
For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.
Known Issues
This table correlates the core version to the first ISE or Vivado tools release version in which it was included.
| Core Version | ISE Version | Vivado Version |
| v11.5 updated | ISE 14.5 | NA |
| v11.5 | ISE 14.4 | 2012.4 |
| v11.4 | ISE 14.2 | 2012.2 |
| v11.3 | ISE 14.1 | 2012.1 |
| v11.2 | ISE 13.4 | NA |
| v11.1 | ISE 13.1 | NA |
The following table provides known issues for the Ethernet 1000BASE-X PCS/PMA or SGMII core starting with v11.1 released in ISE Design Suite 13.1. For previous version of the core, refer to IP Release Notes Guide for the release notes answer record by version.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Article Number | Article Title | Version Found | Version Resolved |
| (Xilinx Answer 55360) | mmcm_locked not connected to GT tx_startup_fsm and rx_startup_fsm | v11.5 | work-around in answer record |
| (Xilinx Answer 55367) | 7 Series GTP and GTH - Update to RX termination | v11.5 | work-around in answer record |
| (Xilinx Answer 57166) | Updates to 7 series reset logic | v11.4 | ISE 14.5, v11.5 |
| (Xilinx Answer 53779) | Virtex-7 GTH Transceiver - RX Reset Sequence Requirement for Production Silicon | v11.4 | ISE 14.5, v11.5 |
| (Xilinx Answer 53561) | Artix-7 - RX Reset Sequence Requirement for Production Silicon | v11.4 | ISE 14.5, v11.5 |
| N/A | Synchronization logic added to 7-Series GT tx_startup_fsm and rx_startup_fsm inputs | v11.4 | ISE 14.5, v11.5 |
| (Xilinx Answer 53444) | After disabling AN, AN sequences may still be transmitted if core has not gained Synchronization yet | v11.4 | ISE 14.5, v11.5 |
| (Xilinx Answer 52780) | 7 Series GTX Transceivers - Update needed to target Production Silicon | v11.4 | ISE 14.4, v11.5 |
| (Xilinx Answer 52237) | 7 Series Devices - SGMII LVDS Interface - Updated needed to Asynchronous data path constraint | v11.4 | ISE 14.4, v11.5 |
| (Xilinx Answer 52135) | 7 Series - 500ns delay needed for GTTXRESET and GTRXRESET | v11.4 | ISE14.4, v11.5 |
| (Xilinx Answer 51975) | SGMII LVDS interface support for Artix-7 and Zynq devices | v11.4 | Not Resolved |
| (Xilinx Answer 51040) | 1000BASE-X - Status Vector Reports incorrect value for Auto-Negotiation Pause Ability | v11.2 | v11.4rev1 |
| (Xilinx Answer 50446) | Artix-7 - Missing TXOUTCLK BUFG | v11.3 | v11.4 |
| (Xilinx Answer 50328) | Update to reset logic for 7-Series SGMII with Elastic Buffer | v11.3 | v11.4 |
| (Xilinx Answer 47358) | Virtex-6 - Core will not auto-negotiate - TX data is corrupted | v11.1 | Not Resolved |
| (Xilinx Answer 47665) | Spartan-6 - Timing Errors maybe seen with Example Design | v11.3 | Not Resolved |
| (Xilinx Answer 47526) | Vivado 2012.1 - CRITICAL WARNING messages seen in example design | v11.3 | v11.3rev1 |
| (Xilinx Answer 47666) | Vivado 2012.1 - Guidance for Simulating Ethernet IP cores | v11.3 | N/A |
| (Xilinx Answer 35338) | Meeting GMII setup and hold times on an external interface when targeting Spartan-6 FPGAs | v11.1 | Not Resolved |
| (Xilinx Answer 46123) | Changes required to implement on 7-Series General ES silicon | v11.2 | v11.3 |
| (Xilinx Answer 45676) | Functional simulation failure when using 1000 BASE-X and VHDL | v11.2 | v11.3 |
| (Xilinx Answer 44937) | Changes required to implement the core on 7-Series Initial ES silicon | v11.1 | Not Resolved |
| (Xilinx Answer 43058) | Why does the Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices? | v11.1 | v11.2 |
| (Xilinx Answer 42672) | 7 Series Transceiver Wrapper - GT Port Name Changes in ISE 13.2 | v11.1 | v11.2 |
| (Xilinx Answer 43421) | GMII_RX_ER not asserted when link lost during frame | v11.1 | v11.2 |
| (Xilinx Answer 42842) | PLLREFCLK selection change causing simulation issue in ISE Design Suite 13.1 | v11.1 | v11.2 |
| (Xilinx Answer 43059) | Error - Invalid target device when running Virtex-7 Example design in 13.2 and later | v11.1 | v11.2 |
| (Xilinx Answer 44958) | Example Design Simulation Does Not Work in ISE 13.2/13.3 | v11.1 | v11.2 |
| (Xilinx Answer 39193) | GTP/GTX Physical DRC failure in MAP | v10.5 | v11.1 |
Revision History
08/20/2013 - Added 57166
07/25/2012 - Updated for 14.2 release
05/08/2012 - Initial release
| AR# 47524 | |
|---|---|
| Date | 08/20/2013 |
| Status | Active |
| Type | Release Notes |
| IP | |