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AR# 47531

Zynq-7000 AP SoC, SDIO - DMA Burst Transactions Alignment And Length Requirements

Description

The length of a DMA burst must be an aligned multiple of 4 bytes to avoid overwriting data in the DMA buffer.

Solution

Impact:

Minor

Work-around:

Ensure that all buffers are a multiple of 4 bytes except for the last buffer which can be any size.

Configurations Affected:

System that use the SDIO controller with the ADMA2 mode.

Device Revision(s) Affected: All, no plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences

 

The SD Host Controller Specification Version 2.00 defines the ADMA2 buffer descriptors and the buffers they point to as being 4-byte aligned; however, the length of each DMA entry can be an arbitrary number of bytes from 1 to 64KB. The controller does not properly handle ADMA2 writes to the card from host memory if the length is not a multiple of 4 bytes. The following example demonstrates the issue.

Descriptor table:

ADDR

LENGTH

DATA

0x1000

4 bytes

0x0123_4567

0x2000

3 bytes

0xABCD_DEAD

0x3000

4 bytes

0x8912_2345


When the ADMA2 operation is initiated, the controller fetches 4 bytes of data from address 0x1000 and pushes the data into location 0 of its internal FIFO (each location is 32 bits wide). That is followed by the next descriptor data being fetched from address 0x2000 and the data being copied in location 1. Since location 1 is not completely filled (only 3 bytes are valid), the pointer is not incremented. The last descriptor data is fetched from address 0x3000 and the data is copied in location 1. The 3 bytes which had existed in location 1 are erroneously overwritten.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47531
Date Created 05/24/2012
Last Updated 05/22/2013
Status Active
Type Design Advisory
Devices
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q