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AR# 47532

Zynq-7000 AP SoC, SDIO - Software Reset Sequence to Avoid Interconnect Hang


The SDIO controller requires that the SDIO clockbe active in order to write to the software resets CMD andDAT. If the SDIO clock is not active, the controller andinterconnect willhang.



Minor, refer to the Work-around.

Enable the SDIO clock beforeissuing aSoft reset to the controller

Configurations Affected:

Systems that use the SDIO controller.

Device Revision(s) Affected: All, no plan to fix. Refer to (Xilinx Answer 47916) Zynq-7000 Design Advisory Master Answer Record

Work-around Detail:Host Driver Software Flow.

Optional: CMD and DAT resets:
This option precedes the Host Driver flow, below, if the Host Driver issues CMD and DAT resets during host controller initialization. If Host Driver issues only Soft Reset for ALL during host controller initialization, then this option is not needed. SDIO clock is needed to clear soft reset CMD and DAT bits.

1) Enable the SDIO clock.
2) Perform CMD and DAT resets. Write 1 then 0 to sdio.Clock_Control_Timeout_control_Software_reset[25, 26].

Example: Host Driver Flow:

1) Wait for card insertion. Configure Card Detect Interrupt.
2) On card insertion, perform Soft Reset ALL. Write 1 then 0 to sdio.Clock_Control_Timeout_control_Software_reset[24].
3) Enable host interrupts and Enable the SDIO Clock.
4) Initialize SD Card.

Soft Reset for ALL:
Asserting the Software_Reset_for_All will reset all of the SDIO registers, including the sdio.Clock_Control_Timeout_control_Software_reset register itself. After the reset, the Driver shall enable the SDIO clock.

Updated August 20, 2012

AR# 47532
Date 03/01/2013
Status Active
Type Design Advisory
  • Zynq-7000