AR# 47532


Zynq-7000 SoC, SDIO - Software Reset Sequence to Avoid Interconnect Hang


The SDIO controller requires that the SDIO clock be active in order to write to the software resets CMD and DAT.

If the SDIO clock is not active, the controller and interconnect will hang.



Minor, refer to the Work-around.

Enable the SDIO clock before issuing a Soft reset to the controller

Configurations Affected:

Systems that use the SDIO controller.

Device Revision(s) Affected:All, no plan to fix. Refer to (Xilinx Answer 47916) Zynq-7000 Design Advisory Master Answer Record
Work-around Detail:Host Driver Software Flow.

Optional: CMD and DAT resets:

This option precedes the Host Driver flow, below, if the Host Driver issues CMD and DAT resets during host controller initialization. 

If Host Driver issues only Soft Reset for ALL during host controller initialization, then this option is not needed. SDIO clock is needed to clear soft reset CMD and DAT bits. 

1) Enable the SDIO clock.
2) Perform CMD and DAT resets. Write 1 then 0 to sdio.Clock_Control_Timeout_control_Software_reset[25, 26].

Example: Host Driver Flow:

1) Wait for card insertion. Configure Card Detect Interrupt.

2) On card insertion, perform Soft Reset ALL. Write 1 then 0 to sdio.Clock_Control_Timeout_control_Software_reset[24].

3) Enable host interrupts and Enable the SDIO Clock.

  • The SDIO_CLK_CTRL register is @0XF8000150
  • Bit 0 is for SD0 Clk control (0: disable and 1:enable)
  • Bit 1 is for SD1 Clk control (0: disable and 1:enable)

4) Initialize SD Card.

Soft Reset for ALL:

Asserting the Software_Reset_for_All will reset all of the SDIO registers, including the sdio.Clock_Control_Timeout_control_Software_reset register itself. 

After the reset, the Driver shall enable the SDIO clock.

AR# 47532
Date 03/19/2020
Status Active
Type Design Advisory
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