The Sticky Pipeline Advance bit in the DBGDSCR register enables the debugger to detect whether the processor is idle. The CPU does not implement accesses to DBGDRCR via the debug APB interface, so the debugger is unable to clear the Sticky Pipeline Advance bit.
Minor. The Sticky Pipeline Advance bit concept is unusable.
Systems that use one or both ARM processors.
Device Revision(s) Affected:
|All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.|
The Sticky Pipeline Advance register (bit 25 of the DBGDSCR register) enables the debugger to detect whether the processor is idle. This bit is set to 1 every time the processor pipeline retires one instruction. A write to DBGDRCR clears this bit. The issue is that the Cortex-A9 does not implement any debug APB access to DBGDRCR to clear the bit.
Minor. Due to the issue, the Sticky Pipeline Advance bit in the DBGDSCR cannot be cleared by the external debugger.