UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47559

Zynq-7000 AP SoC, APU - MRC and MCR Instructions are not Counted in Event 0x68

Description

The MRC and MCR instructions are not counted in the total number of instructions passing through the Register rename pipeline stage. The values of event 0x68 and PMUEVENT[9:8] are imprecise.

Solution

Impact:

Minor. The count of event 0x68 and PMUEVENT[9:8] are imprecise, omitting the number of MCR and MRC instructions. The inaccuracy of the total count depends on the rate of MRC and MCR instructions in the code.

Work-around:

No work-around is possible to achieve the functionality of counting how many instructions are precisely passing through the register rename pipeline stage when the code contains some MRC or MCR instructions.

Configurations Affected:

Systems that use one or both ARM processors.

Device Revision(s) Affected: All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.

 

No work-around is possible to achieve the functionality of counting how many instructions are precisely passing through the register rename pipeline stage when the code contains some MRC or MCR instructions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47559
Date Created 05/30/2012
Last Updated 06/04/2013
Status Active
Type Design Advisory
Devices
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q