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  3. AR# 47560: Zynq-7000 SoC, APU - Read Accesses to a DBGPRSR or DBGOSLSR Register by the DAP Controller can Generate an Unexpected Undefined Exception

AR# 47560

Zynq-7000 SoC, APU - Read Accesses to a DBGPRSR or DBGOSLSR Register by the DAP Controller can Generate an Unexpected Undefined Exception

Description

When a CP14 read command accesses a DBGPRSR or DBGOSLSR register with the control/status DbgSwEnable bit set = 0, the system generates an unexpected UNDEF exception, even in privileged mode. 

The user can set the DbgSwEnable bit = 1 before reading one of these registers and then set the bit = 0 when the read is complete.

Solution

Impact:

Minor. DBGPRSR and DBGOSLSR registers are mainly used for debug across unsupported power-down sequences.

Work-around:

The user can set the DbgSwEnable bit = 1 before reading one of these registers and then set the bit = 0 when the read is complete.

Configurations Affected:

Systems that use one or both ARM processors.

Device Revision(s) Affected:All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.

Impact Details

The DBGPRSR and DBGOSLSR registers are intended to be used as part of debug process that spans from power-down to power-up. However, the power down/up functionality is not supported.

Note: The DbgSwEnable bit is in the Control/Status Word register. This register and the DBGPRSR/DBGOSLSR registers are accessible by the DAP controller.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 SoC Devices - Silicon Revision Differences N/A N/A
AR# 47560
Date 05/25/2018
Status Active
Type Design Advisory
Devices