When a read (cacheable or not) with Normal Memory attributes is received by the L2 cache controller, hazard checking is performed on the read with the active writes in the store buffer. If an address match is detected, the read is stalled until the write completes. However, a continuous flow of writes can stall a read targeting the same memory area.
Impact: |
Trivial. When the conditions above are met, the read might be stalled till the write flow stops. Note that this issue does not lead to any data corruption. Furthermore, normal software code is not expected to contain long write sequence like the one causing this issue. |
Work-around: |
There is no work-around for this issue and none is expected to be necessary. |
Configurations Affected: |
Systems that use one or both ARM processors. |
| Device Revision(s) Affected: | All, no plan to fix. Refer to Zynq-7000 Device Advisory Master Answer Record |
When a read (cacheable or not) with Normal Memory attributes is received by the L2 Controller, hazard checking is performed on the read with the active writes in the store buffer. If an address match is detected, the read is stalled until the write completes. Due to this issue, a continuous flow of writes can stall a read targeting the same memory area.
| AR# 47562 | |
|---|---|
| Date | 08/06/2012 |
| Status | Active |
| Type | Design Advisory |
| Devices |
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