AR# 47563

Zynq-7000 SoC, APU - L2 Cache Controller can Prefetch across 4 KB Boundary with Offset Set to 23

Description

When prefetch is enabled and the prefetch offset is equal to 23 (0x17), then the L2 cache controller prefetches across a 4 KB address boundary. This can cause system issues because those cache line-fills can target a new 4 KB page of memory space, regardless of page attribute settings in the L1 MMU.

The offset values for the prefetch unit can be set from 0 to 31, but to avoid prefetching across the 4 KB boundary, it must never be set to 23. The default value is 0 and enables the next cache line to be prefetched.

Solution

Impact:	Trivial. The issue is easily avoided.
Work-around:	The offset for the Prefetch (which can take a value between 0 and 31) should never be 23. The default value is 0 which enables the next catch line to be Prefetched.
Configurations Affected:	Systems that use the processors L2 cache with prefetching enabled.
Device Revision(s) Affected:	All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.

This problem occurs when both of the following conditions are met:

* One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or Prefetch Control Register) is set.

* The Pre-fetch offset bits are programmed with value 23 (5b10111).

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
47916	Zynq-7000 SoC Devices - Silicon Revision Differences	N/A	N/A

AR# 47563
Date	06/13/2018
Status	Active
Type	Design Advisory
Devices	XA Zynq-7000 Zynq-7000 Zynq-7000Q

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