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  1. Xilinx - All Programmable
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  3. AR# 47564: Zynq-7000 AP SoC, DDR - I/O Buffers do not Support External VREF

AR# 47564

Zynq-7000 AP SoC, DDR - I/O Buffers do not Support External VREF

Description

DDR I/O buffers (DDRIOB) use differential input receivers for which one input to the receiver is connected to the data input and the other is connected to a voltage reference pin called VREF (set to half of the DDR VCC I/O voltage).

VREF needs to be supplied from the internal voltage source because the external VREF feature for DDRIOB is not supported.

Solution

Impact:
Minor. Use the internal VREF reference.
Work-around:
Use the internal VREF reference, see the Solution section for more information.
Configurations
Affected:
Systems that use the PS DDR memory controller.
Device Revision(s) Affected: Refer to Zynq-7000 Device Advisory Master Answer Record
Use the Internal VREF feature. To enable internal VREF:
  • Set DDRIOB_DDR_CTRL.VREF_EXT_EN to 00 (disconnect I/Os from external signal)
  • Set DDRIOB_DDR_CTRL.VREF_SEL to the appropriate voltage setting depending on the DDR standard. (VREF = Vcco_ddr / 2)
  • Set DDRIOB_DDR_CTRL.VREF_INT_EN to 1 to enable the internal VREF generator
AR# 47564
Date 11/12/2012
Status Active
Type Design Advisory
Devices
  • Zynq-7000