The AXI interfaces between PS and PL are enabled upon completion of the BootROM. Software must assert the AXI interface resets early in the execution of the FSBL.
Software must always use proper reset and configuration procedures starting-up the PL AXI interfaces.
Impact: Trivial. You should never assume that the AXI interfaces are enabled and always use proper procedures when configuring and starting the PL.
Work-around: Restore the SLCR.FPGA_RST_CTRL register to its reset value early in the first stage boot loader.
Configurations Affected: All.
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences
Restore the SLCR.FPGA_RST_CTRL register to its reset value early in the first stage boot loader.