Description

There is a delay in updating the SPI/QSPI RxFIFOs "not empty status" bit. 

This can cause polling software to erroneously assume that there is still data in the RxFIFO when there is none and cause the RxFIFO to under-run. 

This leads to invalid data being read. 

To avoid the situation, software should read the not empty status bit twice. 

This allows enough time for the controller to update the status bit. 

This behavior has been detected in the SPI controller software, but not in the Quad-SPI controller software.

Solution

Impact: Minor. FIFO under-run may occur which leads to invalid data being read.

Work-around: Read the status register twice and use the value of the not empty status bit of the second read.

Configurations Affected: Systems that use the SPI or Quad-SPI controller.

Device Revision(s) Affected: No Plan to Fix. Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.

Read the status register twice and use the value of the not empty status bit of the second read.

Linked Answer Records

Master Answer Records