The DDR controller in LPDDR2 mode does not issue automatic long/short calibration commands (ZQCL/ZQCS) during normal operation. Calibration is done during the DDR initialization phase, but temperature and voltage usually change over time and calibration must be performed periodically. Software must issue explicit ZQ calibration commands to maintain peak performance of the DRAM I/O buffers.
|Minor. A work-around is supported.|
Issue periodic ZQCL/ZQCS commands manually.
Systems that use the PS DDR memory controller in LPDDR2 mode.
Device Revision(s) Affected:
|Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record|
Temperature and voltage can change during normal operation. Without the calibration command being issued, there will potentially be a shift in the data eye caused by loss of the impedance tolerances due to temp and voltage variation. This could result in data corruption. Xilinx device drivers implement a work-around for this issue.
The work-around for this is to issue periodic ZQCL/ZQCS commands manually, through software control using the MRW interface to the DRAM. This is available by writing to the APB register, reg_ddrc_mr_data in the DRC.ERRATA ITEM source.