In linear mode, the Quad-SPI controller might hang when there is a high volume of memory requests. Reduce the data rate through the controller using the baud rate divisor. The potential for a hang does not appear when the device is accessed during the boot process.
Impact: Minor. Work-around affects throughput.
Work-around: Reduce the clock divider, refer to the Solution section for more information.
Configurations Affected: Systems that use the Quad-SPI memory controller in linear addressing mode outside of boot.
Device Revision(s) Affected: Refer to Zynq-7000 Device Advisory Master Answer Record
The boot from Quad-SPI operation is not affected by this issue. For other Quad-PSI applications operating in linear address mode, high throughput can hang the PS system. The problem could not be reproduced with a clock divider value equal to or larger than 16. The controller must be in linear addressing mode for the system hang to occur. The occurrence of this issue depends on the frequency and type of memory requests issued by the PS system.
For Linear Quad-SPI mode, the flow of data through the controller can be lowered by changing the controllers baud rate divider using bits [5:3] of the configuration register. Set the baud rate divider to 16 (Config_reg[5:3] = 011) or a larger value.