The LPDDR2 per-bank refresh function is not supported.
The work-arounds are explained below.
Systems that use the DDR memory controller in LPDDR2 mode with eight banks.
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.|
The best overall work-around is to avoid using per-bank refresh, and to use all-bank refresh instead (i.e., set reg_ddrc_per_bank_refresh = 0).
If this is not acceptable, the individual issues can be worked around as follows: