The LPDDR2 per-bank refresh function is not supported.
Impact: | Minor. |
Work-arounds: | The work-arounds are explained below. |
Configurations Affected: | Systems that use the DDR memory controller in LPDDR2 mode with eight banks. |
Device Revision(s) Affected: | All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences. |
The best overall work-around is to avoid using per-bank refresh, and to use all-bank refresh instead (i.e., set reg_ddrc_per_bank_refresh = 0).
If this is not acceptable, the individual issues can be worked around as follows:
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
47916 | Zynq-7000 SoC Devices - Silicon Revision Differences | N/A | N/A |
AR# 47580 | |
---|---|
Date | 05/25/2018 |
Status | Active |
Type | Design Advisory |
Devices |