AR# 47581

Zynq-7000 SoC, DDR PS - Read operations malfunction when they follow an MRW within 128 DDR clock cycles

Description

The MRW operation requires time to execute. If an MRR or normal memory read operation occurs within 128 DDR clock cycles after the MRW cycle, the data from the MRR or normal memory read operation is corrupted.

The corruption can be avoided by not issuing either read operation within the 128 clock cycle period after the MRW operation.

Solution

Impact:	Minor. The manual calibration algorithm from Xilinx which uses MRW operations takes this issue into account.
Work-around:	There are two work-arounds as described in the Work-around Details.
Configurations Affected:	System that use the DDR memory controller.
Device Revision(s) Affected:	All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.

Work-around Details

There are two work-arounds for this issue:

Do not execute an MRR or read command within 128 cycles of an MRW operation. This work-around takes advantage of the auto-correction mechanism built in the controller.
Set the Mode register set command update delay value, reg_ddrc_t_mod, in the controller to a value larger than or equal to 128.
This forces all MRW operations to have duration equal to the programmed a value larger than or equal to 128.
This forces all MRW operations to have duration equal to the programmed value. The Xilinx Zddr tool sets this value to 512.

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
47916	Zynq-7000 SoC Devices - Silicon Revision Differences	N/A	N/A

AR# 47581
Date	06/13/2018
Status	Active
Type	Design Advisory
Devices	Zynq-7000 XA Zynq-7000 Zynq-7000Q

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