Description

The MRW operation requires time to execute. If an MRR or normal memory read operation occurs within 128 DDR clock cycles after the MRW cycle, the data from the MRR or normal memory read operation is corrupted. 

The corruption can be avoided by not issuing either read operation within the 128 clock cycle period after the MRW operation.

Solution

Work-around Details

There are two work-arounds for this issue:

• Do not execute an MRR or read command within 128 cycles of an MRW operation. This work-around takes advantage of the auto-correction mechanism built in the controller.
• Set the Mode register set command update delay value, reg_ddrc_t_mod, in the controller to a value larger than or equal to 128.
  This forces all MRW operations to have duration equal to the programmed a value larger than or equal to 128.
  This forces all MRW operations to have duration equal to the programmed value. The Xilinx Zddr tool sets this value to 512.

Linked Answer Records

Master Answer Records