The MRW operation requires time to execute. If an MRR or normal memory read operation occurs within 128 DDR clock cycles after the MRW cycle, the data from the MRR or normal memory read operation is corrupted.
The corruption can be avoided by not issuing either read operation within the 128 clock cycle period after the MRW operation.
|Impact:||Minor. The manual calibration algorithm from Xilinx which uses MRW operations takes this issue into account.|
|Work-around:||There are two work-arounds as described in the Work-around Details.|
|Configurations Affected:||System that use the DDR memory controller.|
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.|
There are two work-arounds for this issue: