The DDR controller in LPDDR2 mode does not issue the ZQCL calibration command after exiting the self-refresh operation.
Although not required by the DRAM JEDEC specifications, some vendors expect that the ZQCL command will be issued after self-refresh exit and before any other memory requests can be processed.
The work-around for this issue is for software to periodically issue ZQCS commands while the LPDDR2 device is in self-refresh mode.
Impact: | Minor, refer to the Work-around Details. |
Work-arounds: | Software periodically issues a ZQSC command. |
Configurations Affected: | Systems that use the DDR memory controller in LPDDR2 mode. |
Device Revision(s) Affected: | Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences. |
Description Details
The PS DDR controller does not issue the ZQCL calibration command after exiting the self-refresh operation.
The ZQ Calibration commands are used to calibrate the LPDDR2 output drivers over process, temperature, and voltage.
Although not required by the DRAM JEDEC specifications, some vendors (for example Micron) expect that the ZQCL command will be issued after self-refresh exit and before any other memory requests can be processed.
Impact Details
Without the calibration command being issued, there will potentially be a shift in the data eye caused by loss of the impedance tolerances due to temp and voltage variation.
This could result in data corruption. Xilinx device drivers implement a work-around for this issue.
Work-around Details
The work-around for this problem is for software to periodically issue ZQCS commands manually while the LPDDR2 device is in self-refresh mode.
This is achieved through the DRAM MRW interface and by writing to the DDR Controller register, reg_ddrc_mr_data.
If the temperature derating feature is enabled, then additional steps are needed:
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
47916 | Zynq-7000 AP SoC Devices - Silicon Revision Differences | N/A | N/A |
AR# 47582 | |
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Date | 06/13/2018 |
Status | Active |
Type | Design Advisory |
Devices |