UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47582

Zynq-7000 AP SoC, DDR - In LPDDR2 Mode, ZQCL Command is not Issued after Self-Refresh Exit

Description

The DDR controller in LPDDR2 mode does not issue the ZQCL calibration command after exiting the self-refresh operation.

Although not required by the DRAM JEDEC specifications, some vendors expect that the ZQCL command will be issued after self-refresh exit and before any other memory requests can be processed.

The work-around for this issue is for software to periodically issue ZQCS commands while the LPDDR2 device is in self-refresh mode.

Solution

Impact:

Minor, refer to the Work-around Details.

Work-arounds:

Software periodically issues a ZQSC command.

Configurations Affected:

Systems that use the DDR memory controller in LPDDR2 mode.

Device Revision(s) Affected:

Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.


Description Details

The PS DDR controller does not issue the ZQCL calibration command after exiting the self-refresh operation. 

The ZQ Calibration commands are used to calibrate the LPDDR2 output drivers over process, temperature, and voltage. 

Although not required by the DRAM JEDEC specifications, some vendors (for example Micron) expect that the ZQCL command will be issued after self-refresh exit and before any other memory requests can be processed.

Impact Details

Without the calibration command being issued, there will potentially be a shift in the data eye caused by loss of the impedance tolerances due to temp and voltage variation. 

This could result in data corruption. Xilinx device drivers implement a work-around for this issue.

Work-around Details

The work-around for this problem is for software to periodically issue ZQCS commands manually while the LPDDR2 device is in self-refresh mode. 

This is achieved through the DRAM MRW interface and by writing to the DDR Controller register, reg_ddrc_mr_data.


If the temperature derating feature is enabled, then additional steps are needed:

  1. Disable temp_derating before entering self-refresh mode.
  2. Set the reg_ddrc_dis_dq bit = 1 before entering self-refresh mode (disables CAM de-queuing of memory commands).
  3. Enable temp_derating after coming out of self-refresh.
  4. Issue a derating request through software.
  5. Set the reg_ddrc_dis_dq bit = 0 and allow the normal traffic to resume.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47582
Date Created 05/24/2012
Last Updated 11/18/2014
Status Active
Type Design Advisory
Devices
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q