PLD instructions prefetch and allocate any data marked as Write-Back (either Write-Allocate or Non-Write-Allocate, Shared or Non-Shared), regardless of the processor configuration settings, including the Data Cache Enable bit value.
This can create data consistency issues. This issue does not occur if the data cache is enabled.
The work-around requires software to set a bit in an undocumented Control register. Setting this bit causes all PLD instructions to be treated as NOPs.
Minor. Unexpected memory cacheability aliasing is created which might result in data consistency issues, see Impact Details for more information.
Refer to the Work-around Details section below for information on writing to the undocumented control registers.
|Device Revision(s) Affected:|
All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.
This issue is not expected to have any significant impact. The Data Cache is expected to be enabled early in the boot process and not disabled later.
So, only boot-up code would be impacted, but such code is usually carefully controlled and not expected to contain any PLD instruction while Data Cache is not enabled.
In the case where a system is impacted by this issue, a software workaround is available which consists of setting bit  in the undocumented Control register, which is placed in CP15 c15 0 c0 1.
This bit needs to be written with the following Read-Modify-Write code sequence:
Setting this bit causes all PLD instructions to be treated as NOPs, with the consequence that code sequences usually using the PLDs, such as the memcpy() routine, might suffer from a performance drop.
So, if this work-around is applied, Xilinx strongly recommends restricting its usage to periods of time where the Data Cache is disabled.