AR# 47589: Zynq-7000 SoC, Signals - Programming GPIOB to HSTL18 when VCCO_MIO is at 2.5/3.3V can damage IOB receiver
Zynq-7000 SoC, Signals - Programming GPIOB to HSTL18 when VCCO_MIO is at 2.5/3.3V can damage IOB receiver
I/O buffers for MIO pins (GPIOBs) must not be programmed to use VREF (for differential HSTL receivers) if VCCO_MIO is 2.5V or 3.3V. Long term damage can occur to the I/O buffer if the following conditions are true:
At least one I/O of a particular bank is setup as LVCMOS25, LVCMOS33 or LVTTL using the slcr.MIO_PIN_*[IO_Type] control bit.
Internal VREF voltage is enabled using slcr.GPIOB_CTRL[VREF_SW_EN] register control bit and VREF pin is set to 0.9V.
One I/O (in the same bank as the IO from #1) is configured as HSTL18 with output 3-stated and pad driven to 2.5V or higher level.
GPIOBs must not be programmed as VREF for differential receivers if VCCO_MIO is 2.5V or 3.3V.