When boot mode JTAG, NOR or NAND is selected, the Quad-SPI HOLD_B pin is held low and the controller cannot communicate with the Quad-SPI device. This is because MIO pin 5 (part of the Boot_Mode select) is strapped low.
When other boot modes are selected, MIO pin 5 is strapped high and there are no issues.
Do not use a Quad-SPI device in the system when JTAG, NOR or NAND is the boot device.
The Quad-SPI devices have a dual-purpose pin: HOLD_B/DQ3. An active low HOLD_B gates CLK and DIN and 3-states DOUT when CS_B is active.
HOLD_B/DQ3 is mapped to MIO pin 5 which is pulled high when Quad-SPI boot mode is selected. In this case, the Quad-SPI works as expected.
However, certain boot modes, such as JTAG, pull MIO low. If QSPI is used in these other boot modes, it leads to the assertion of HOLD_B in certain Quad-SPI protocol phases, which will hang the Quad-SPI transaction.
Minor. Only in rare cases is it desirable to include a Quad-SPI device and not boot from it.
Attach a Quad-SPI device only when it is the boot device.
Systems that use the Quad-SPI interface, but do not boot in Quad-SPI mode.
|Device Revision(s) Affected:||Refer to (Xilinx Answer 47916)|