2. Support
  3. AR# 4760: 4.1i XC4000E MAP - To control whether a BUFGP or a BUFGS is used, a BUFG must be LOC'd before MAP.
  4. AR# 47605: Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - RBAR support in IES Silicon

AR# 47605

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - RBAR support in IES Silicon

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 does not support RBAR in IES Silicon.

Solution

The optional PCI Express Resizable BAR (RBAR) capability is not supportedthrough configuration for users targeting IES silicon. The RBAR feature can be initiated after the FPGA has been configured.This is a known issue and will be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47441 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 47605
Date 05/20/2012
Status Active
Type Known Issues
IP