Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)
Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 corerequires PF0_PM_CSR_NOSOFTRESET to be tied to 1'b1 in IES Silicon.
The generated core files default the value toPF0_PM_CSR_NOSOFTRESET1'b1. Users targeting IES silicon should not change this setting from the default value.This is a known issue and will be fixed in a future release of the core.
NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
05/08/2012 - Initial release