Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)
Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 core does not supportD1 low power device state for users targeting IES silicon.
This is a known issue and will be fixed in a future release of the core.
NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
05/08/2012 - Initial release