Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)
The default example design generated with the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 core does not support Address Aligned mode.
The alignment mode is configurable within the CORE Generator interface. Address Aligned mode is not supported with the PIO example design. This is a known issue and will be fixed in a future release of the core.
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
05/08/2012 - Initial release