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AR# 47611

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Bit File Generation Support

Description

Bitfile generation for the design with Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 core is not supported without locking down system reset.

Solution

Users who want to create a bitfile are first required to lock down the system reset to a pin. If you are targeting a Xilinx Development Board, the default IP output locks down the system reset accordingly and bitfile generation is supported in this configuration.

To get rid of the error message, when generating a bitfile for non Xilinx Development Board and without locking down the system reset, add "-ise" to the bitgen options.

Revision History
05/08/2012 - Initial release

Linked Answer Records

Master Answer Records

AR# 47611
Date Created 06/28/2012
Last Updated 08/26/2013
Status Active
Type General Article
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)