UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 47627: 7 Series Integrated Block for PCI Express v1.4 (ISE 14.1) - Incorrect completion packets generation for interface width 128-bit with configuration other than x8Gen2

AR# 47627

7 Series Integrated Block for PCI Express v1.4 (ISE 14.1) - Incorrect completion packets generation for interface width 128-bit with configuration other than x8Gen2

Description

Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

Interface width 128-bit with configuration other than x8 Gen2 has an issue with completion packets.

Solution

This is a known issue and will be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40469 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 47627
Date 05/20/2012
Status Active
Type Known Issues
Page Bookmarked