AR# 47628


7 Series Integrated Block for PCI Express v1.4 (ISE 14.1 / Vivado 2012.1) - Timing violations in certain IP configurations


Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

There are certain IP configurations that do not meet timing.


This is a known issue and will be fixed in a future release of the core. If you run intotiming violations with theimplementation of the default core generation, please create aWebCase with Xilinx Technical Supportand submit the XCO file and the timing report.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

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Master Answer Records

AR# 47628
Date 05/20/2012
Status Active
Type Known Issues
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