Cases have been seen where BUFIODQS clock nets have not been routed when using the OPTDELAY resource.
This is required to match the delay of associated BUFR clocks when both are clocking the same I/O components.
There are two known causes:
Correct routing of BUFDQS net using the OPTDELAY resource:
A DRC check will be created to catch incorrectly routed BUFIODQS nets.
Meanwhile the design can be examined in FPGA Editor if incorrect routing is suspected.
Remove any unnecessary timing constraints to prevent the rip up and reroute behavior mentioned above.