2. Support
  3. AR# 4766: F1.5F2.1i ABEL - Abl2edif creates an incorrect netlist when the underscore character is used at the end of a signal name: give based:24 error in translate
  4. AR# 47665: LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.3 (ISE 14.1) - Timing errors might be seen with example design if targeting a Spartan-6 device

AR# 47665

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.3 (ISE 14.1) - Timing errors might be seen with example design if targeting a Spartan-6 device

Description

If targeting Spartan-6 devices with the Ethernet 1000BASE-X PCS/PMA or SGMII v11.3 in ISE 14.1 software, timing errors similar to the following might be seen when implementing the example design:

"Timing constraint: ts_tx_clk = PERIOD TIMEGRP "tx_logic" 8 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

3809 paths analyzed, 1863 endpoints analyzed, 49 failing endpoints
49 timing errors detected. (49 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 10.057ns."

Solution

These timing errors are currently under investigation. If you encounter timing errors, please open a WebCase with Xilinx Technical Support to explore solutions.
AR# 47665
Date 12/15/2012
Status Active
Type General Article
Tools
IP