AR# 47666: Vivado Design Suite 2012.1 - Guidance for Simulating Ethernet IP Cores
Vivado Design Suite 2012.1 - Guidance for Simulating Ethernet IP Cores
For the 2012.1 release of this core, the simulation process requires additional guidance. The Vivado design tools currently deliver IP simulation scripts when you elaborate the core which assume the core is delivered as a Verilog netlist; since the IP netlist is not automatically generated by the Vivado IP flow, the user must first manually synthesize the core, then run write_verilog to generate the netlist before the simulation can be run.
The required steps are as follows:
The following procedure assumes you have a Vivado project with the IP already added to it from the Vivado IP Catalog.
To run Functional Simulation:
In the hierarchy view of the project, click to select the core.
Right-click the core and select Generate.
In the pop-up menu that appears, select "All", and click OK.
This will generate all the simulation support scripts for the core.
In the hierarchy view, once again select the core,
Click Run Synthesis.
Once complete, select "open synthesis netlist".
In the Tcl console enter:
write_verilog -mode funcsim <corename>.v (corename should be the user-defined name given to the IP when it is initially added to the original project, e.g., tri_mode_eth_mac_v5_3_0)
This will write a netlist to the main project directory and return the created file name.
This netlist is required by the simulation script, so copy this file to: