UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - All Programmable
  2. Support
  3. AR# 47671: Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Incorrect reset of ARI Capable Hierarchy bit in the SR-IOV control register

AR# 47671

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Incorrect reset of ARI Capable Hierarchy bit in the SR-IOV control register

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The ARI Capable Hierarchy bit in the SR-IOV control register is incorrectly reset by a function level reset of the physical function.

Solution

This is a known issue to be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47441 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 47671
Date 05/20/2012
Status Active
Type Known Issues
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
Page Bookmarked