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AR# 47684

LogiCORE IP XAUI - Release Notes and Known Issues for v10.x

Description

This answer record contains the Release Notes for the LogiCORE IP XAUI Core and includes the following:

  • New Features
  • Supported Devices
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator interface known issues, and design tools requirements, see the IP Release Notes Guide.

For LogiCORE IP XAUI v11.0 and later Release Notes, see (Xilinx Answer 54669).

For LogiCORE IP XAUI Frequently Asked Questions (FAQ), see (Xilinx Answer 33596).

Solution

New Features in Latest v10.4 Core

  • ISE 14.2 and Vivado 2012.2 tools support
  • Incorporated latest Transceiver Wizard wrappers
  • Artix-7 FPGA support in ISE and Vivado design tools
  • Zynq-7000 device support in ISE design tools

Supported Devices in ISE for Latest v10.4 Core

  • All 7 series devices
  • Zynq-7000 devices
  • All Virtex-6 devices
  • Spartan-6 devices
  • Spartan-6 XC LXT (Speed grade -3)
  • Spartan-6 XQ LXT (Speed grade -3)
  • Virtex-5 devices
  • Virtex-5 LXT/SXT/TXT/FXT
  • Defense Grade Virtex-5Q LXT/SXT/FXT
  • Virtex-4 devices
  • Virtex-4 FX
  • Defense Grade Virtex-4Q FX
  • Defense Grade Virtex-4QR XQR FX
  • Space-Grade Virtex-4QV

Supported Devices in Vivado for latest v10.4 Core

  • All 7 series devices

Note: For a complete part and package support list, see the Xilinx CORE Generator interface (under 'Supported Families') for XAUI.

For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

Known Issues

This table correlates the core version to the first ISE or Vivado tools release version in which it was included.

Core Version ISE Version Vivado Version
v10.4 (Rev. 1) ISE 14.5 NA
v10.4 ISE 14.2 2012.2
v10.3 ISE 14.1 2012.1
v10.2 ISE 13.4 N/A
v10.1 ISE 13.1 N/A


The following table provides known issues for the XAUI core starting with v10.1 released in ISE Design Suite 13.1. For previous versions of the core, refer to the IP Release Notes Guide for the release notes answer record by version.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 58083) Update to 7-Series GTX Transceiver attribute - RXDFEXYDEN v10.4 Work-around in answer record
(Xlinx Answer 56312) Update to 7 Series GTP/GTH reset logic v10.4 (Rev. 1) Work-around in answer record
(Xilinx Answer 55446) 7 Series GT Transceivers - Required Updates v10.4 v10.4 (Rev. 1)
(Xilinx Answer 50848) 7 Series GT Transceivers - Reset might be needed after disabling Loopback v10.3 Work-around in answer record
(Xilinx Answer 50397) 7 Series GT Transceivers - The core fails to achieve alignment after link partner is reset or a cable re-plug v10.3 v10.4
(Xilinx Answer 47644) ISE - 7 Series - Timing failures might be seen in XAUI Example Design v10.3 Work-around in answer record
(Xilinx Answer 47690) VHDL wrappers need update to RXCDR_CFG attribute v10.3 v10.4
(Xilinx Answer 46707) Required changes to implement the core on 7 Series General ES devices v10.2 v10.3
(Xilinx Answer 45405) Required changes to implement the core on 7 Series Initial ES devices v10.2 Work-around in answer record
(Xilinx Answer 43215) Virtex-6 devices - TX lanes sometimes do not align successfully v10.1 Work-around in answer record
(Xilinx Answer 40897) Xs are seen in ModelSim 6.6c functional or timing simulation v10.1 Work-around in answer record
(Xilinx Answer 45816) GUI does not correctly restrict selection of 20G data rate and non 802.3 State Machines v10.2 v10.2rev1
(Xilinx Answer 42673) 7 Series Transceiver Wrapper - GTX Port Name Changes in ISE 13.2/13.3 v10.1 v10.2
(Xilinx Answer 42850) Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices? v10.1 v10.2
(Xilinx Answer 42842) 7 Series GTX Transceiver - PLLREFCLK selection change causing simulation issue in ISE Design Suite 13.1 v10.1 v10.2
(Xilinx Answer 42842) 7 Series - PLLREFCLK selection change causing simulation issue v10.1 v10.2
(Xilinx Answer 44392) 7 Series - GTRXRESET pin must be asserted until the PLL has locked v10.1 v10.2
(Xilinx Answer 43482) 7 Series GTX Transceiver Reset Requirements Upon Configuration v10.1 v10.2
(Xilinx Answer 44858) 7 Series GTX Transceiver - GTn_RXCDRRESET and GTn_RXBUFRESET port connection changes v10.1 v10.2


Vivado Design Suite Specific Known Issues

Answer Record
Title
Version Found
Version Resolved
(Xilinx Answer 50795)
Vivado, 7 Series - Timing failures might occur in XAUI Example Design
v10.4
Not Resolved
(Xilinx Answer 47666)
Vivado 2012.1 - Guidance for Simulating Ethernet IP cores
v10.3
N/A

Linked Answer Records

Child Answer Records

AR# 47684
Date Created 05/02/2012
Last Updated 06/19/2014
Status Active
Type Release Notes
IP
  • XAUI