This answer record contains the Release Notes for the LogiCORE IP RXAUI Core and includes the following:
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.
For RXAUI v3.0 and later Release Notes, see (Xilinx Answer 54249).
New Features in Latest v2.4 Core
Supported Devices
Note: For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.
Known Issues
This table correlates the core version to the first ISE or Vivado tools release version in which it was included.
| Core Version | ISE Version | Vivado Version |
| v2.4 (Rev 1) | ISE 14.5 | NA |
| v2.4 | ISE 14.3 | 2012.3 |
| v2.3 | ISE 14.1 | 2012.1 |
| v2.2 | ISE 13.4 | NA |
| v2.1 | ISE 13.1 | NA |
| v1.2 | ISE 12.1 | NA |
| v1.1rev1 | ISE 11.5 | NA |
| v1.1 | ISE 11.3 | NA |
NOTE: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| (Xilinx Answer 58083) | Update to 7-Series GTX Transceiver attribute - RXDFEXYDEN | v2.1 | Work-around in answer record |
| (Xilinx Answer 56313) | Update to 7 Series GTP reset logic | v2.4 (Rev. 1) | Work-around in answer record |
| (Xilinx Answer 55445) | 7 Series - Required GTP/GTX and GTH transceiver updates | v2.4 | v2.4 (Rev. 1) |
| (Xilinx Answer 52414) | 7 Series GT Transceivers - Updates maybe need to GT wrapper files | v2.4 | v2.4 (Rev. 1) |
| (Xilinx Answer 50848) | 7 Series GT Transceivers - Reset might be needed after disabling Loopback | v2.3 | v2.4 |
| (Xilinx Answer 46705) | Targeting 7 Series FPGAs General ES hardware | v2.2 | v2.3 |
| (Xilinx Answer 46524) | Receive data errors might be seen in Marvell mode | v2.2 | v2.3 |
| (Xilinx Answer 46523) | Alignment Fails to Complete at Startup | v2.2 | v2.3 |
| (Xilinx Answer 46483) | 7 Series - Core fails to regain Synchronization after link partner restarts transmission | v2.2 | v2.3 |
| (Xilinx Answer 45731) | 7 Series - Timing Failure in Marvell Mode | v2.2 | v2.3 |
| (Xilinx Answer 43482) | 7 Series GTX Transceiver Reset Requirements Upon Configuration | v2.1 | v2.2 |
| (Xilinx Answer 44393) | 7 Series GTX Transceiver - GTRXRESET pin must be asserted until the PLL has locked | v2.1 | v2.2 |
| (Xilinx Answer 42842) | 7 Series GTX Transceiver - PLLREFCLK selection change causing simulation issue in ISE Design Suite | v2.1 | v2.2 |
| (Xilinx Answer 42850) | 7 Series Example Design Fails in BitGen | v2.1 | v2.2 |
| (Xilinx Answer 42674) | 7 Series Transceiver Wrapper - GTX Port Name Changes in 13.2 ISE design tools | v2.1 | v2.2 |
| (Xilinx Answer 40865) | Only the FlipChip Virtex-7 and Kintex-7 device packages are supported | v2.1 | v2.2 |
| (Xilinx Answer 39493) | Virtex-6 - GTX Transceiver Delay Aligner Errata and Work-around | v1.2 | v2.1 |
| (Xilinx Answer 33893) | Virtex-6 - MAP errors for some device packages | v1.1 | v1.2 |
| (Xilinx Answer 34160) | Virtex-6 - MMCM can cause DRC errors | v1.1 | v1.1rev1 |
| (Xilinx Answer 33649) | Virtex-6 - GTX default setting for TXDIFFCTRL could result in electrical idle condition | v1.1 | v1.1rev1 |
| (Xilinx Answer 33488) | Virtex-6 - GTX powerdown reset logic should be updated | v1.1 | v1.1rev1 |
| (Xilinx Answer 33486) | Virtex-6 - GTX wrappers Update needed for reset logic in block level | v1.1 | v1.1rev1 |
Vivado Design Suite Specific Known Issues
| (Xilinx Answer 50494) | Potential Naming conflict for Verilog Modules | v2.3 | v2.4 |
| (Xilinx Answer 47666) | Vivado 2012.1 - Guidance for Simulating Ethernet IP cores | v2.3 | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 55445 | RXAUI v2.4, 7 Series - Required GTP/GTX and GTH transceiver updates | N/A | N/A |
| 56313 | RXAUI v3.0 rev1, v2.4 rev1 - Update to 7 Series GTP reset logic | N/A | N/A |
| AR# 47692 | |
|---|---|
| Date | 10/29/2013 |
| Status | Active |
| Type | Release Notes |
| IP |
|