This answer record contains the Release Notes for the LogiCORE IP 10-Gigabit Ethernet MAC v11.x core and contains the following information:
For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide (XTP025):
New Features for v11.6 Core:
New Features for v11.5 Core:
New Features for v11.4 Core:
Supported Devices for v11.6 Core:
Note: For a complete part and package support list, please see the Xilinx CORE Generator interface (under 'Supported Families') for the 10-Gigabit Ethernet MAC Core.
For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.
This table correlates the core version to the first ISE or Vivado design tools release version in which it was included.
|Core Version||ISE Tool Version||Vivado Tool Version|
|v11.6||ISE 14.5||Not Supported|
|v11.3||ISE 14.1||Not supported in Vivado Design Suite 2012.1|
Note: For release notes and known issues for v12.0 and later of the core, see (Xilinx Answer 54252).
The following table provides known issues for the 10-Gigabit Ethernet MAC core, starting with v11.1, initially released in ISE Design Suite 13.1.This is the first version to support 7 series devices and have an AXI interface. For earlier versions of the core using the legacy user interface, please refer to IP Release Notes Guide for the release notes answer record by version.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|(Xilinx Answer 56069)||ISE - Marginal timing sometimes seen when targeting Spartan-6 devices||v11.6||Work-around in AR|
|N/A||Receive Out Of bounds frames were not being counted in statistics if followed immediately by another frame.||v11.5||v11.6|
|N/A||Received 12 byte undersized frame marked good||v11.5||v11.6|
|N/A||Transmitter hangs when sending 63 byte frame with inband FCS passing||v11.5||v11.6|
|N/A||Occasionally first frame transmitted after power up seen to have incorrect FCS||v11.5||v11.6|
|N/A||10GEMAC does not enforce minimum IFG on TX after erroring frame||v11.5||v11.6|
|N/A||Received frames longer than maximum length in MTU mode were being marked as good.||v11.4||v11.5|
|N/A||1519 byte VLAN frame sometimes marked as errored on receive||v11.4||v11.5|
|(Xilinx Answer 53357)||TX Pause Frames not transmitted while paused||v11.1||v11.5|
|(Xilinx Answer 47740)||Frame following abort/underrun may be dropped||v11.2||v11.3|
|(Xilinx Answer 45984)||Custom preamble dropped under certain conditions||v11.2||v11.3|
|(Xilinx Answer 45081)||Core Returns Incorrect Version Number||v11.2||v11.3|
|N/A||Local Fault sequence after max length frame can clobber following frame of any size with max frame size error||v11.2||v11.3|
|N/A||Transmitting large jumbo frames in WAN mode could cause a hang||v11.2||v11.3|
|(Xilinx Answer 40898)||When Inband FCS and WAN or IFG Delay is enabled occasionally an extra 4 bytes of IFG is transmitted||v11.1||v11.2|
|N/A||In-band FCS and DIC cannot be enabled together on config vector||v11.1||v11.2|
|N/A||AXI TX FIFO in example design can get stuck FULL||v11.1||v11.2|
|N/A||Functional simulation does not work on VCS||v11.1||v11.2|
|N/A||AXI FIFO in example design can repeat the last word of data||v11.1||v11. 2|
Vivado Design Suite Specific Known Issues
|(Xilinx Answer 52348)||Artix-7 Devices - Vivado 2012.3 - opt_design -remap option maybe needed to avoid timing errors||Not Resolved|