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AR# 47699

MIG 7 Series - Input clock period set in mig.prj not maintained when generating the design using "Verify Pin Changes and Update Design"

Description

Version Found: v1.5
Version Resolved: v1.6

An issue can occur when a core is regenerated via the "Verify Pin Changes and Update Design" flow or via the command line:
coregen -p coregen.cgp -b mig_7series_v1_4.xco

The tool sometimes changes the input clock period setting in the regenerated core from the original setting.

Solution

When regenerating a core in MIG 7 series, verify that the input clock period setting has not changed. 

This would effect the CLKIN_PERIOD and PLL mult/divide parameters in the top level RTL, input clock period constraint in the UCF, and the input clock period settings in the mig.prj and datasheet.txt files.


To work around this issue, manually change these settings back to the original settings.

This issue is resolved in MIG 7 series v1.6 available with ISE Design Suite 14.2.

AR# 47699
Date Created 07/10/2012
Last Updated 08/21/2014
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
  • Artix-7
IP
  • MIG 7 Series